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p3p623s05a/b and p3p623s09a/b timing-safe? peak emi reduction ic ?2010 scillc. all rights reserved. publication order number: july 2010 C rev. 1 p3p623s05/d general features clock distribution with timing-safe? peak emi reduction input frequency range: 20mhz - 50mhz multiple low skew timing-safe? outputs: p3p623s05: 5 outputs p3p623s09: 9 outputs supply voltage: 3.3v0.3v packaging information: p3p623s05: 8 pin tssop p3p623s09:16 pin tssop true drop-in solution for zero delay buffer functional description p3p623s05/09 is a versatile, 3.3v zero-delay buffer designed to distribute timing-safe? clocks with pea k emi reduction. p3p623s05 is an eight-pin version, accepts one reference input and drives out five low -skew timing-safe? clocks. p3p623s09 accepts one referenc e input and drives out nine low-skew timing-safe? clo cks. all parts have on-chip plls that lock to an input c lock on the clkin pin. the pll feedback is on-chip and is obtained from the clkout pad, internal to the devic e. multiple p3p623s05 / p3p623s09 devices can accept the same input clock and distribute it. in this cas e, the skew between the outputs of the two devices is guaranteed to be less than 700ps. all outputs have less than 200ps of cycle-to-cycle jitter. the input and output propagation delay is guarantee d to be less than 350ps, and the output-to-output skew is guaranteed to be less than 250ps. refer spread spectrum control and input-output skew table for deviations and input-output skew for p3p623s05a/b and p3p623s09a/b devices. p3p623s05/09 operates from a 3.3v supply and is available in tssop package, as shown in the orderin g information table. application p3p623s05/09 is targeted for use in displays and memory interface systems. general block diagram pll clkout clk1 clk2 clk3 clk4 p3p623s05 a /b clkin clkin clkout pll mux clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 select input decoding s2 s1 p3p623s09 a /b
p3p623s05a/b and p3p623s09a/b rev. 1 | page 2 of 11 | www.onsemi.com spread spectrum frequency generation the clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase t he edge rates also get faster. analysis shows that a s quare wave is composed of fundamental frequency and harmonics. the fundamental frequency and harmonics generate the energy peaks that become the source of emi. regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from t he equipment. in fact, the peak level allowed decrease s as the frequency increases. the standard methods of reducing emi are to use shielding, filtering, multi -layer pcbs, etc. these methods are expensive. spread spectrum clocking reduces the peak energy by reduci ng the q factor of the clock. this is done by slowly modulating the clock frequency. the p3p623s05/09 us es the center modulation spread spectrum technique in which the modulated output frequency varies above a nd below the reference frequency with a specified modulation rate. with center modulation, the averag e frequency is the same as the unmodulated frequency and there is no performance degradation. timing-safe? technology timing-safe? technology is the ability to modulate a clock source with spread spectrum technology and maintain synchronization with any associated data p ath.
p3p623s05a/b and p3p623s09a/b rev. 1 | page 3 of 11 | www.onsemi.com pin configuration for p3p623s05a/b pin description for p3p623s05a/b pin # pin name type description 1 clkin 1 i external reference clock input, 5v tolerant input 2 clk1 2 o buffered clock output 4 3 clk2 2 o buffered clock output 4 4 gnd p ground 5 clk3 2 o buffered clock output 4 6 vdd p 3.3v supply 7 clk4 2 o buffered clock output 4 8 clkout 4 o buffered clock output.internal feedback on this pin. notes: 1. weak pull down 2. weak pull-down on all outputs 3. weak pull-up on these inputs 4. buffered clock output is timing-safe? clkin clk1 1 2 3 4 5 6 7 8 gnd clk3 vdd clkout clk2 clk4 p3p623s05a/b
p3p623s05a/b and p3p623s09a/b rev. 1 | page 4 of 11 | www.onsemi.com 1 2 3 4 13 14 15 16 p3p623s09a/b 5 6 7 8 9 10 11 12 pin configuration for p3p623s09a/b pin description for p3p623s09a/b pin # pin name pin type description 1 clkin 1 i external reference clock input, 5v tolerant inp ut 2 clka1 2 o buffered clock bank a output 4 3 clka2 2 o buffered clock bank a output 4 4 vdd p 3.3v supply 5 gnd p ground 6 clkb1 2 o buffered clock bank b output 4 7 clkb2 2 o buffered clock bank b output 4 8 s2 3 i select input, bit 2. see select input decoding table for p3p623s09a/b for more details 9 s1 3 i select input, bit 1. see select input decoding table for p3p623s09a/b for more details 10 clkb3 2 o buffered clock bank b output 4 11 clkb4 2 o buffered clock bank b output 4 12 gnd p ground 13 vdd p 3.3v supply 14 clka3 2 o buffered clock bank a output 4 15 clka4 2 o buffered clock bank a output 4 16 clkout 2 o buffered clock output.internal feedback on this pin. notes: 1. weak pull down 2. weak pull-down on all outputs 3. weak pull-up on these inputs 4. buffered clock output is timing-safe? clka3 clka4 clkb3 clkb4 vdd gnd s1 clkout vdd gnd clkb1 clkb2 clka1 clkin clka2 s2
p3p623s05a/b and p3p623s09a/b rev. 1 | page 5 of 11 | www.onsemi.com select input decoding table for p3p623s09a/b s2 s1 clk a1 - a4 clk b1 - b4 clkout 1 output source pll shut-down 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n note1: this output is driven and has an internal fe edback for the pll. the load on this output can be adjusted to change the skew between the reference a nd the output spread spectrum control and input-output skew table frequency (mhz) device deviation ( %) input-output skew (t skew ) 32 p3p623s05a / 09a 0.25 0.125 p3p623s05b / 09b 0.5 0.25 note: t skew is measured in units of the clock period absolute maximum ratings symbol parameter rating unit vdd supply voltage to ground potential -0.5 to +4.6 v vin dc input voltage (clkin) -0.5 to +7 t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114- b) 2 kv note: these are stress ratings only and are not imp lied for functional use. exposure to absolute maxim um ratings for prolonged periods of time may affect device reliability. operating conditions parameter description min max unit vdd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) -40 + 85 c c l load capacitance 30 pf c in input capacitance 7 pf
p3p623s05a/b and p3p623s09a/b rev. 1 | page 6 of 11 | www.onsemi.com electrical characteristics parameter description test conditions min typ max unit v il input low voltage 5 0.8 v v ih input high voltage 5 2.0 v i il input low current v in = 0v 50 a i ih input high current v in = vdd 100 a v ol output low voltage 6 i ol = 8ma 0.4 v v oh output high voltage 6 i oh = -8ma 2.4 v i dd supply current unloaded outputs 15 ma z o output impedance 23 w notes: 5. clkin input has a threshold voltage of vd d/2 6. parameter is guaranteed by design and characterization. not 100% tested in production. switching characteristics parameter test conditions min typ max unit input frequency 20 50 mhz output frequency 30pf load 20 50 mhz duty cycle 7,8 = (t 2 / t 1 ) * 100 measured at vdd/2 40 50 60 % output rise time 7, 8 measured between 0.8v and 2.0v 2.5 ns output fall time 7, 8 measured between 2.0v and 0.8v 2.5 ns output-to-output skew 7, 8 all outputs equally loaded 250 ps delay, clkin rising edge to clkout rising edge 8 measured at vdd /2 350 ps device-to-device skew 8 measured at vdd/2 on the clkout pins of the device 700 ps cycle-to-cycle jitter 7, 8 loaded outputs 200 ps pll lock time 8 stable power supply, valid clock presented on clkin pin 1.0 ms notes: 7. all parameters specified with 30pf loaded outputs. 8. parameter is guaranteed by design and characterization. not 100% tested in production.
p3p623s05a/b and p3p623s09a/b rev. 1 | page 7 of 11 | www.onsemi.com switching waveforms duty cycle timing all outputs rise/fall time output - output skew input - output propagation delay t 2 t 1 v dd /2 v dd /2 v dd /2 output t 3 output t 4 0.8v 2v 0.8v 2v t 5 output output v dd /2 v dd /2 t 6 output input v dd /2 v dd /2
p3p623s05a/b and p3p623s09a/b rev. 1 | page 8 of 11 | www.onsemi.com device - device skew input - output skew test circuit typical example of timing-safe? waveform t skew - one clock cycle n=1 t skew + input timing-safe? output t skew represents input-output skew when spread spectrum is on for example, t skew = 0.125 for an input clock12mhz, translates in to (1/12mhz) * 0.125=10.41ns input clkout with ssoff input timing-safe? clkout t 7 clkout, device 1 v dd /2 v dd /2 clkout, device 2 v dd gnd clk load output 0.1uf +3.3v 0.1uf +3.3v v dd
p3p623s05a/b and p3p623s09a/b rev. 1 | page 9 of 11 | www.onsemi.com e h a a1 a2 d b c l q e package information 8-lead tssop (4.40-mm body) symbol dimensions inches millimeters min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.033 0.037 0.85 0.95 b 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.114 0.122 2.90 3.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.028 0.50 0.70 0 8 0 8
p3p623s05a/b and p3p623s09a/b rev. 1 | page 10 of 11 | www.onsemi.com 16-lead tssop (4.40-mm body) d e h d a a1 b e q l c a2 pin 1 id 1 89 16 seating plane symbol dimensions inches millimeters min max min max a 0.043 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.193 0.201 4.90 5.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.030 0.50 0.75 0 8 0 8
p3p623s05a/b and p3p623s09a/b on semiconductor and are registered trademarks of semiconductor componen ts industries, llc (scillc). scillc reserves the ri ght to make changes without further notice to any products herein. sci llc makes no warranty, representation or guarantee regarding the suitability of its products for any p articular purpose, nor does scillc assume any liability arisi ng out of the application or use of any product or circuit, and specifically disclaims any and all lia bility, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applica tions and actual performance may vary over time. al l operating parameters, including typicals must b e validated for each customer application by customer 's technical experts. scillc does not convey any l icense under its patent rights nor the rights of ot hers. scillc products are not designed, intended, or auth orized for use as components in systems intended fo r surgical implant into the body, or other applicat ions intended to support or sustain life, or for any oth er application in which the failure of the scillc p roduct could create a situation where personal inju ry or death may occur. should buyer purchase or use scillc pro ducts for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs , damages, and expenses, and reasonable attorney fe es arising out of, directly or indirectly, any claim of person al injury or death associated with such unintended or unauthorized use, even if such claim alleges tha t scillc was negligent regarding the design or manufacture o f the part. scillc is an equal opportunity/affirmat ive action employer. u.s patent pending; timing-sa fe and active bead are trademarks of pulsecore semicon ductor, a wholly owned subsidiary of on semiconduct or. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ordering code ordering code marking package type temperature p3p623s05bg-08tr adq 8-pin 4.4-mm tssop C tape & reel, green 0c to +70 a microdot placed at the end of last row of marki ng or just below the last row toward the center of package indicates pb-free

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